1. Field of the Invention
Embodiments of the present invention relate generally to integrated circuit fabrication and packaging and, more specifically, to a removable substrate for controlling warpage of an integrated circuit package
2. Description of the Related Art
Integrated circuit (IC) fabrication is a multi-step sequence that includes processes such as patterning, deposition, etching, and metallization. Typically, in the final processing steps, the resulting IC die are separated and packaged. IC packaging serves several purposes, including providing an electrical interface with the die, providing a thermal medium through which heat may be removed from the die, and/or providing mechanical protection for the die during subsequent usage and handling.
One type of IC packaging technique is referred to as “flip chip” packaging. In flip chip packaging, after the metallization process is complete, solder bump structures (e.g., solder balls, pads, etc.) are deposited on the die, and the die is separated from the wafer (e.g., via dicing, cutting, etc.). The die is then inverted and positioned on a substrate so that the solder bumps align with electrical connections formed on the substrate. Heat is applied via a solder reflow process to re-melt the solder bumps and attach the die to the substrate. The die/substrate assembly may further be underfilled with a non-conductive adhesive to strengthen the mechanical connection between the die and the substrate.
IC fabrication techniques have enabled the production of larger-sized die having increasingly high transistor densities. Consequently, IC packaging techniques have encountered challenges for providing packaging capable of supporting the requisite number of electrical connections. Specifically, as the size of the die and number of electrical connections to the die is increased, the size of the package generally is increased. Further, as package size is increased, the thermal properties of the die and packaging materials become a more important factor.
One relevant thermal property of the die and packaging materials is the coefficient of thermal expansion (CTE). In flip chip packaging, for example, during the solder reflow process, the die is attached to the substrate at an elevated temperature. Upon cooling, a mismatch between the CTE of the die and the CTE of the substrate may cause the substrate to warp, thereby reducing the planarity of the IC package and preventing electrical connections from being formed with the IC package. Additionally, warping of the IC package typically degrades the electrical connections provided between the die and the substrate. Consequently, IC packages that experience significant warping are oftentimes discarded for being outside of specification requirements.
In order to reduce warping of the IC package, some conventional packaging techniques permanently bond a substrate (commonly referred to as a “lid”) to the IC package. For example, in many techniques, a lid having a thickness of less than 1 millimeter is bonded on top of one or more IC dies included in the IC package. A heat sink is then positioned on top of the lid in order to dissipate heat generated during operation of the IC die(s).
One disadvantage to this technique is that the lid insulates the IC die(s) from the heat sink, which reduces the rate at which heat can be removed from the IC package via the heat sink. Consequently, although bonding the lid to the IC package reduces the amount of warping of the IC package, the lid may cause the IC die(s) to overheat and/or reduce the overall performance characteristics of the IC die(s).
As the foregoing illustrates, more effective techniques for reducing the amount of warping in IC packages would be useful.